TTTC's Electronic Broadcasting Service

CALL FOR PARTICIPATION

Scope

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), microbumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Program

The workshop program contains the following elements:

Keynote Address: tbd
Two sessions with in total seven paper presentations
Two panel-discussion sessions

On �3D Memories: What Is Coming And How Are We Going To Test That?�
On �2.5D-SICs: Do We Need To Test The Interposer, And If So, How?�

A special session on the status of IEEE P1838 test access standard
A special session on ongoing PhD research in 3D-Test
Continuous display of table-top demos and posters

For the detailed version of the program, please visit the workshop website: http://3dtest.tttc-events.org

Key Dates

Early discount registration: September 26th, 2014 (Please make sure to use this offer if you plan to attend)

NOTE: The workshop can still accommodate a few Posters and Table-Top Demos. Please submit them via our website (submission reopened) and/or send them to erik.jan.marinissen@imec.be via e-mail before October 6, 2014.

Additional Information

Yervant Zorian � General Chair

Synopsys

700 East Middlefield Road

Mountain View, CA 94043-4033, USA

Tel.: +1 (650) 584-7120

E-mail: yervant.zorian@synopsys.com

Erik Jan Marinissen � Program Chair

IMEC

Kapeldreef 75

B-3001 Leuven, Belgium

Tel.: +32 (0)16 28-8755

E-mail: erik.jan.marinissen@imec.be

Committee

top

General Chair:

Y. Zorian � Synopsys (US)

Program Chair:

E.J. Marinissen � IMEC (BE)

Finance Chair:

B. Eklow � Cisco Systems (US)

Finance Vice-Chair / Arrangements:

J. Potter � ASSET InterTech (US)

Publicity Chair:

F. von Trapp � 3DInCites (US)

Publication Chair:

L. Ciganda � Politecnico di Torino (IT)

Web Chair:

G. Jervan � Tallinn Univ. of Techn. (EE)

Program Committee Members:

S. Adham � TSMC (CAN)
V. Agrawal � Auburn Univ. (US)
S. Bhatia � Google (US)
K. Chakrabarty � Duke Univ. (US)
S. Chakravarty � Avago Tech (US)
K.Y. Chung � Samsung (KR)
C.J. Clark � Intellitech (US)
E. Cormack � DfT Solutions (UK)
A. Cron � Synopsys (US)
A. Crouch � ASSET InterTech (US)
D. Domke � Texas Instruments (US)
M.-L. Flottes � LIRMM (FR)
P. Franzon � NC State Univ. (US)
S.K. Goel � TSMC (US)
S. Hamdioui � TU Delft (NL)
M. Higgins � Analog Devices (IRL)
C.-L. Hsu � ITRI (TW)
S.-Y. Huang � NTHU (TW)
M. Hutner � Teradyne (CAN)
H. Jun � SK hynix (KR)
S. Kameyama � Fujitsu (JP)
M. Knox � IBM (US)
M. Laisne � Qualcomm (US)
S. Lecomte � Intel (DE)
K.H. Lee � GigaLane (KR)
C.M. Li � NTU (TW)
M. Loranger � FormFactor (US)
A. Majumdar � Xilinx (US)
T.M. Mak � GlobalFoundries (US)
T. McLaurin � ARM (US)
B. Nadeau-Dostie � Mentor Graph. (US)
C. Papameletis � Cadence (US)
B. Patti � Tezzaron Semiconductor (US)
M. Ricchetti � AMD (US)
S. Shaikh � Broadcom (US)
T. Th�rigen � Cascade Microtech (DE)
P. Vivet � CEA-Leti (FR)
M. Wahl � Univ. Siegen (DE)
Q. Xu � Chinese Univ. Hong Kong (HK)

For more information, visit us on the web at: http://3dtest.tttc-events.org

3D-TEST'14 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).